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| HT46R652 A/D with LCD Type 8-Bit OTP MCU Technical Document * Tools Information * FAQs * Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series - HA0047E An PWM application example using the HT46 series of MCUs Features * Operating voltage: * Buzzer output * On-chip crystal, RC and 32768Hz crystal oscillator * Power-down function and wake-up features reduce fSYS=4MHz: 2.2V~5.5V fSYS=12MHz: 3.3V~5.5V * 32 bidirectional I/O lines * Two external interrupt inputs * Two 16-bit programmable timer/event counters with power consumption * 16-level subroutine nesting * 8-channel 12-bit resolution A/D converter * 16-channel 8-bit PWM output shared with 16 I/O lines * Bit manipulation instruction * 16-bit table read instruction * Up to 0.33ms instruction cycle with 12MHz system PFD (programmable frequency divider) function * LCD driver with 413 or 404 segments (logical output option for SEG0~SEG23) * 8K16 program memory * 3848 data memory RAM * PFD for sound generation * Real Time Clock (RTC) * 8-bit RTC prescaler * Watchdog Timer clock * 63 powerful instructions * All instructions in 1 or 2 machine cycles * Low voltage reset/detector function * 100-pin QFP package General Description The HT46R652 is an 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D product applications that interface directly to analog signals and which require an LCD Interface. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, Power-down and wake-up functions, in addition to a flexible and configurable LCD interface enhance the versatility of these devices to control a wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc. for both the industrial and home appliance application areas. Rev. 1.00 1 December 19, 2006 HT46R652 Block Diagram In te rru p t C ir c u it P ro g ra m EPROM P ro g ra m C o u n te r STACK IN T C TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M U X M U P r e s c a le r X P A 4 /T M R 0 P A 7 /T M R 1 fS Y S /4 32768Hz fS YS In s tr u c tio n R e g is te r MP M U RTC X DATA M e m o ry W DT T im e B a s e M U X fS YS /4 RTC OSC OSC3 OSC4 W DT OSC In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n MUX PW M PC C ,PD C STATUS PC ,PD 8 -C h a n n e l A /D C o n v e rte r BP PBC PB LCD M e m o ry P o rt B P B 0 /A N 0 ~ P B 7 /A N 7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 /B Z /B Z /P /T /IN /IN /T FD MR0 T0 T1 MR1 P o rt C P o rt D P C 0 /P W M 0 ~ P C 7 /P W M 7 P D 0 /P W M 8 ~ P D 7 /P W M 1 5 S h ifte r OSC2 OSC4 OS RE VD AV PC PD VS PC PD OS DD VD VD S /A VS VS C3 S D S C1 /V R E F D D S VSS ACC PAC PA H ALT P o rt A L C D D r iv e r E N /D IS C O M 0~ COM2 C O M 3/ SEG 40 SEG 0~ SEG 39 L V D /L V R Rev. 1.00 2 December 19, 2006 HT46R652 Pin Assignment SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 OSC4 OSC3 VDD OSC2 OSC1 RES P A 0 /B Z P A 1 /B Z PA2 P A 3 /P F D P A 4 /T M R 0 100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81 80 79 78 PA PB PB PB PB PB PA PA7 PB PB PB 5 /IN 0 /A 1 /A 2 /A 3 /A 4 /A 6 /IN /T M 5 /A 6 /A 7 /A VR AV AV V W W M M M M M M V V V V W P P P P P P 0 /P 1 /P /P W /P W /P W /P W /P W /P W PD PD PC PC P C 0 /P PD PD D2 D3 D4 D5 D6 D7 T0 N0 N1 N2 N3 N4 T1 R1 N5 N6 N7 EF DD SS NC NC SS M8 M9 10 11 12 13 14 15 DD SS SS DD M0 1 2 3 4 5 6 7 8 9 77 76 75 74 73 72 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 71 70 69 68 67 H T46R 652 1 0 0 Q F P -A 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 SEG COM COM COM COM C2 C1 V2 V1 VMA VLC NC NC PC7 PC6 PC5 PC4 PC3 PC2 PC1 /P W /P W /P W /P W /P W /P W /P W M7 M6 M5 M4 M3 M2 D 39 3 /S E G 4 0 X 0 1 2 M1 Rev. 1.00 3 December 19, 2006 HT46R652 Pin Description Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4/TMR0 PA5/INT0 PA6/INT1 PA7/TMR1 I/O Options Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively. Pins PA5, PA6, PA4 and PA7 are pin-shared with INT0, INT1, TMR0 and TMR1 respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once a PB line is selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine if all pins on the port have pull-high resistors. A configuration option determines if all of the pins on this port are to be used as PWM outputs. Individual pins cannot be selected to have a PWM function. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. A configuration option for each pin on this port determines if each pin is to be used as a PWM output. LCD power supply IC maximum voltage connect to VDD, VLCD or V1 Voltage pump SEG40 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are outputs for the LCD panel. LCD driver outputs for the the LCD panel segments. SEG0~SEG23 can be configured as logical outputs via a configuration option. OSC1 and OSC2 are connected to an RC network or external crystal (determined by a configuration option) for the internal system clock. If the RC system clock is selected, OSC2 can be used to measure the system clock at 1/4 frequency. The system clock may also be sourced from the RTC oscillator, in which case these two pins can be left floating. Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to form a system clock source, depending on configuration options. Schmitt trigger reset input, active low Positive power supply Analog positive power supply and A/D converter reference input voltage. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Port C positive power supply Port D positive power supply Negative power supply and analog negative power supply, ground Port C negative power supply, ground Port D negative power supply, ground I/O Wake-up Pull-high Buzzer PFD PB0/AN0~ PB7/AN7 I/O Pull-high PC0/PWM0~ PC7/PWM7 I/O Pull-high PWM PD0/PWM8~ PD7/PWM15 VLCD VMAX V1, V2, C1, C2 COM0~COM2 COM3/SEG40 SEG0~SEG39 I/O Pull-high PWM 3/4 3/4 3/4 1/3 or 1/4 Duty Logical Output I I I O O OSC1 OSC2 I O Crystal or RC OSC3 OSC4 RES VDD AVDD/VREF PCVDD PDVDD VSS/AVSS PCVSS PDVSS Note: I O I 3/4 RTC or System Clock 3/4 3/4 Individual pins on PC cannot be selected as a PWM output, if the PWM configuration option is selected for this port then all pins on PC will be setup as PWM outputs. Rev. 1.00 4 December 19, 2006 HT46R652 Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................300mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-200mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Test Conditions Symbol Parameter VDD VDD AVDD IDD1 Operating Voltage Analog Operating Voltage* Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (fSYS=32768Hz) Standby Current (*fS=T1) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT RC OSC) 3/4 3/4 3/4 3V 5V 3V 5V 5V 3V No load, ADC off 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V No load, system HALT LCD off at HALT No load, system HALT LCD on at HALT, C type No load, system HALT LCD on at HALT, C type No load, system HALT LCD on at HALT, R type, 1/2 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/3 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/2 bias, VLCD=VDD (Low bias current option) No load, system HALT LCD on at HALT, R type, 1/3 bias, VLCD=VDD (Low bias current option) Conditions fSYS=4MHz fSYS=12MHz VREF=AVDD No load, ADC off fSYS=4MHz No load, ADC off fSYS=4MHz No load, ADC off fSYS=12MHz 2.2 3.3 3.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 3 1 3 4 0.3 0.6 3/4 3/4 2.5 10 2 6 17 34 13 28 14 26 10 19 5.5 5.5 5.5 2 5 2 5 8 0.6 1 1 2 5 20 5 10 30 60 25 50 25 50 20 40 Min. Typ. Max. Ta=25C Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IDD2 IDD3 IDD4 ISTB1 ISTB2 ISTB3 ISTB4 Standby Current (*fS=32.768kHz OSC) ISTB5 Standby Current (*fS=32.768kHz OSC) ISTB6 Standby Current (*fS=WDT RC OSC) ISTB7 Standby Current (*fS=WDT RC OSC) Rev. 1.00 5 December 19, 2006 HT46R652 Symbol VIL1 VIH1 VIL2 VIH2 VLVR VLVD IOL1 Parameter Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Voltage Low Voltage Detector Voltage I/O Port (PA, PB) and Segment Logic Output Sink Current I/O Port (PA, PB) and Segment Logic Output Source Current I/O Port (PC, PD) Sink Current 5V IOH2 3V I/O Port (PC, PD) Source Current 5V IOL3 LCD Common and Segment Current LCD Common and Segment Current Pull-high Resistance of I/O Ports 5V VAD VREF DNL INL A/D Input Voltage ADC Input Reference Voltage Range ADC Differential Non-Linear ADC Integral Non-Linear 3/4 3/4 3/4 3/4 3/4 3V 5V AVDD=3V AVDD=5V 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V 3/4 3/4 3/4 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V VOL=0.1VDD VOH=0.9VDD Conditions 3/4 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD Min. 0 0.7VDD 0 0.9VDD 2.7 3.0 6 10 -2 -5 10 25 -10 -25 210 350 -80 -180 20 10 0 1.3 1.5 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3.0 3.3 12 25 -4 -8 20 40 -20 -40 420 700 -160 -360 60 30 3/4 3/4 3/4 3/4 2.5 3/4 0.5 1.5 Max. 0.3VDD VDD 0.4VDD VDD 3.3 3.6 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 50 VREF AVDD AVDD 2 4 12 1 3 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA kW kW V V V LSB LSB Bits mA mA IOH1 IOL2 IOH3 RPH RESOLU Resolution IADC Additional Power Consumption if A/D Converter is Used Note: *fS please refer to clock option of WDT * Voltage level of AVDD and VDD must be the same. Rev. 1.00 6 December 19, 2006 HT46R652 A.C. Characteristics Test Conditions Symbol Parameter VDD fSYS1 System Clock System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency (TMR0/TMR1) Watchdog Oscillator Period 5V tRES tSST tLVR tINT tAD tADC tADCS Note: External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time *tSYS= 1/fSYS1 or 1/fSYS2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 3/4 3/4 3/4 3/4 400 400 3/4 3/4 0 0 45 32 1 3/4 0.25 1 1 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 1 3/4 3/4 80 32 4000 12000 3/4 3/4 4000 12000 180 130 3/4 3/4 2 3/4 3/4 3/4 3/4 kHz kHz Hz Hz kHz kHz ms ms ms *tSYS ms ms ms tAD tAD Min. Typ. Max. Unit Ta=25C fSYS2 fRTCOSC fTIMER tWDTOSC Rev. 1.00 7 December 19, 2006 HT46R652 Functional Description Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter, PC, is 13 bits wide and it controls the sequence in which the instructions stored in the Program Memory are executed. The contents of the PC can specify a maximum of 8192 addresses. T1 T2 T3 T4 T1 T2 After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. S y s te m O S C 2 (R C C lo c k o n ly ) PC T3 T4 T1 T2 T3 T4 PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter *12 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0 Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Time Base Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter+2 *12 #12 *11 #11 *10 #10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 S12 S11 S10 Program Counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits Rev. 1.00 8 December 19, 2006 HT46R652 The lower byte of the PC, known as PCL is a readable and writeable register. Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits which are addressed by the program counter and table pointer. Certain locations in the ROM are reserved for special usage: * Location 000H * Location 008H Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. * Location 00CH Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Location 010H Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H. * Location 014H Location 000H is reserved for program initialization. After a device reset, the program always begins execution at this location. * Location 004H Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H. * Location 018H Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. 000H 004H 008H 00CH 010H 014H 018H n00H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t R T C In te rru p t L o o k - u p ta b le ( 2 5 6 w o r d s ) P ro g ra m M e m o ry Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H. * Table location nFFH 1FFFH L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 1 F Any location in the Program Memory can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH which is the Table Higher-order byte register. Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH register is read only, and the table pointer, TBLP, is a read/write register, indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal Program Memory depending upon the users requirements. Program Memory Instruction(s) TABRDC [m] TABRDL [m] Table Location *12 P12 1 *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *12~*0: Table location bits @7~@0: Table pointer bits P12~P8: Current program counter bits Rev. 1.00 9 December 19, 2006 HT46R652 Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer, SP, which is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction, RET or RETI, the contents of the program counter is restored to its previous value from the stack. After a device reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents a stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost as only the most recent sixteen return addresses are stored. Data Memory - RAM The data memory has a structure of 4318 bits, and is divided into two functional groups, namely the special function registers, 478 bits, and the general purpose data memory, Bank0: 1928 bits and Bank2: 1928 bits most of which are readable/writeable, although some are read only. The special function registers are overlapped in every bank. Any unused remaining space before 40H is reserved for future expanded usage and if read will return a 00H value. The Data Memory space before 40H will overlap in each bank. The general purpose data memory, addressed from 40H to FFH (Bank0; BP=0 or Bank2; BP=2), is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers, MP0 and MP1. After first setting up BP to the value of 01H or 02H to access either bank 1 or bank 2 respectively, these banks must then be accessed indirectly using the Memory Pointer MP1. With BP set to a value of either 01H or 02H, using MP1 to indirectly read or write to the data memory areas with addresses from 40H~FFH, will result in operations to either bank 1 or bank 2. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of BP. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH PW M4 PW M5 PW M6 PW M7 ADRL ADRH ADCR ACSR PW M8 PW M9 PW M 10 PW M 11 PW M 12 PW M 13 PW M 14 PW M 15 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PW M0 PW M1 PW M2 PW M3 IN T C 1 S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H FFH G e n e ra l P u rp o s e D a ta M e m o ry (3 8 4 B y te s ) :U nused R e a d a s "0 0 " RAM Mapping Rev. 1.00 10 December 19, 2006 HT46R652 Indirect Addressing Register Locations 00H and 02H are for indirect addressing registers that are not physically implemented. Any read/write operation to locations [00H] and [02H] accesses the Data Memory locations pointed to by MP0 and MP1 respectively. Reading location 00H or 02H indirectly will return a result of 00H. Writing indirectly will lead to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the Data Memory by combining corresponding indirect addressing registers. MP0 can only be applied to the data memory, while MP1 can be applied to both the data memory and the LCD display memory. Accumulator - ACC The accumulator, ACC, is related to the ALU operations. It is also mapped to location 05H in the Data Memory and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions: * Arithmetic operations - ADD, ADC, SUB, SBC, DAA * Logic operations - AND, OR, XOR, CPL * Rotation - RL, RR, RLC, RRC * Increment and Decrement - INC, DEC * Branch decision - SZ, SNZ, SIZ, SDZ etc. Status Register - STATUS The status register is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, a device power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the precautions should be taken to save it properly. Interrupts The device provides two external interrupts, two internal timer/event counter interrupts, an internal time base interrupt and an internal real time clock interrupt. The interrupt control register 0, INTC0, and the interrupt control register 1, INTC1, both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked as the EMI bit is automatically cleared, which may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the Function The ALU not only saves the results of a data operation but also changes the status register. Bit No. 0 Label C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 Rev. 1.00 11 December 19, 2006 HT46R652 service routine, the EMI bit and the corresponding bit of INTC0 or of INTC1 may be set in order to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts will generate a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the Program Memory. Only the contents of the program counter is pushed onto the stack. If the contents of the register or of the status register is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a an edge transition on INT0 or INT1, when the related interrupt request flag, EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0, is set. The trigger edge type, high to low, low to high, or both low to high and or high to low is determined by configuration option. After the interrupt is enabled, if the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag, EIF0 or EIF1, and EMI bits are all cleared to disable other maskable interrupts. Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4 The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag, T0F; bit 6 of INTC0, which is normally caused by a timer overflow. After the interrupt is enabled, and if the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag, T0F, is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F, bit 4 of INTC1, and its subroutine call location is 10H. The time base interrupt is initialised by setting the time base interrupt request flag, TBF; bit 5 of INTC1, that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag, TBF, is reset and the EMI bit is cleared to disable further maskable interrupts. The real time clock interrupt is initialised by setting the real time clock interrupt request flag, RTF; bit 6 of INTC1, that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag, RTF, is reset and the EMI bit is cleared to disable further maskable interrupts. Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt 0 (1=enabled; 0=disabled) Controls the external interrupt 1 (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ET1I ETBI ERTI 3/4 T1F TBF RTF Function Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Controls the time base interrupt (1=enabled; 0:disabled) Controls the real time clock interrupt (1=enabled; 0:disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) INTC1 (1EH) Register Rev. 1.00 12 December 19, 2006 HT46R652 During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine,a RET or RETI instruction may be executed. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time base interrupt Real time clock interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H which is determined by configuration option. When the device enters the Power Down mode, the RC or crystal oscillator will cease running to conserve power. The 32768Hz crystal oscillator, however, will keep running when the device is in the Power Down mode. If the 32768Hz crystal oscillator is selected as the system oscillator, when the device enters the Power Down mode, the system oscillator keeps running, but instruction execution will cease. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing functions, RTC, time base and WDT, continue to operate even when the system enters the Power Down mode. If the RC oscillator is used, an external resistor connected between pins OSC1 and VSS is required, whose value should range from 24kW to 1MW. The system clock, divided by 4, can be monitored on pin OSC2 if a pull-high resistor is connected. This pin can be used to synchronise external logic. The RC oscillator provides the most cost effective solution. However, as the frequency may vary with VDD, temperature, and process variations, it is therefore not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If a crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors between OSC1 and OSC2 and ground are required. The other oscillator circuit, which is a real time clock, requires a 32768Hz crystal oscillator to be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to start-up quickly by setting the QOSC bit, which is bit 4 of RTCC. It is recommended to turn on the quick start-up function during power on, and then turn it off again after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator, which does not require external components. Although when the system enters the Power Down mode and the system clock stops, the WDT oscillator still operates with a nominal period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. V OSC3 OSC1 470pF DD The EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI bits are all used to control the enable/disable status of the interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags, RTF, TBF, T0F, T1F, EIF1, EIF0 are set, they remain in the INTC1 or INTC0 register respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use a CALL instruction within the interrupt subroutine. This is because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, execution of a CALL in the interrupt subroutine may damage the original control sequence. Oscillator Configuration The device provides three oscillator circuits for the system clock, namely an RC oscillator, a crystal oscillator and an RTC 32768Hz crystal oscillator, the choice of OSC1 OSC4 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r OSC2 C r y s ta l O s c illa to r fS YS /4 OSC2 RC O s c illa to r System Oscillator Note: *32768Hz crystal enable condition: for WDT clock source or for system clock source. Rev. 1.00 13 December 19, 2006 HT46R652 Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. If the internal WDT oscillator, which is an RC oscillator with a nominal period of 65ms at 5V, is selected, it is divided by 212~215 , the actual ratio chosen by configuration option, to get the WDT time-out period. The minimum period for the WDT time-out period is about 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the WDT configuration option, longer time-out periods can be realised. If the WDT time-out is selected as 215, the maximum time-out period is divided by 215~216 about 2.1s~4.3s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the Power Down mode the WDT will stop counting and lose its protecting function. If the device operates in a noisy environment, using the WDT internal RC oscillator is strongly recommended, since the HALT instruction will stop the system clock. The WDT overflow under normal operation initiates a device reset which sets the status bit TO. In the Power Down mode, the overflow initiates a warm reset, in which only the Program Counter and Stack Pointer are reset to zero. To clear the contents of the WDT, there are three methods that can be adopted. These are, an external reset, which is a low level on the RES pin, a software instruction and a HALT instruction. There are two types of software instructions; a single CLR WDT instruction or S y s te m C lo c k /4 ROM Code O p tio n fS D iv id e r fS /2 8 the pair of instructions, CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on a configuration option - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case where the two CLR WDT1 and CLR WDT2 instruction are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. Multi-function Timer The device provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC, the RTC OSC or the instruction clock, which is the system clock divided by 4. The multi-function timer also provides a selectable frequency signal, whose division ratio ranges from fS/22 to fS/28, for LCD driver circuits, and a selectable frequency signal, ranging from fS/22 to fS/29, for the buzzer output selectable via configuration options. It is recommended to select a frequency as close as possible to 4kHz for the LCD driver circuits to obtain the best display clarity. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from 212/fS to 215/fS selected by a configuration option. If a time base time-out occurs, the related interrupt request flag, TBF; bit 5 of INTC1, will be set. If the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. RTC O SC 32768H z W DT OSC 12kH z W DT P r e s c a le r CK M a s k O p tio n W D T C le a r R T CK R T T im e 2 15/fS ~ 2 14/fS ~ 2 13/fS ~ 2 12/fS ~ ou 21 21 21 21 6 5 tR eset /fS /fS 4/f S 3 /fS Watchdog Timer fs D iv id e r P r e s c a le r ROM Code O p tio n T im e B a s e In te r r u p t 2 12/fS ~ 2 15/fS ROM C o d e O p tio n L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9) Time Base Rev. 1.00 14 December 19, 2006 HT46R652 Real Time Clock - RTC The real time clock, RTC, is operated in the same manner as the time base in that it is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215, the value being setup using software. Writing data to the RT2, RT1 and RT0 bits in the RTCC register, provides various time-out periods. If an RTC time-out occurs, the related interrupt request flag, RTF; bit 6 of INTC1, is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 2 8* 2 9* 210* 211* 212 213 214 215 executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and the Stack Pointer, but leaves the others in their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by a configuration option. If awakened by an I/O port stimulus, the program resumes execution at the next instruction following the HALT instruction. Awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, a regular interrupt response takes place. When an interrupt request flag is set before entering the Power Down mode, the system cannot be awakened using that interrupt. If a wake-up events occur, it takes 1024 tSYS (system clock periods) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if a wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power Down mode. Reset There are three ways in which a reset may occur. * RES pin is pulled low during normal operation * RES pin is pulled low when in the Power Down mode * A WDT time-out during normal operation Note: * not recommended to be used Power Down Operation The Power Down mode is entered by the execution of a HALT instruction and results in the following. * The system will cease to run but the WDT oscillator will keep running if the WDT oscillator or the real time clock is selected. * The contents of the Memory and registers remain un- changed. * The WDT will be cleared and starts recounting, if the WDT clock source is sourced from the WDT oscillator or the real time clock oscillator. * All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * The LCD driver will maintain its function if the WDT OSC or RTC OSC is selected. The system will wake up from the Power Down mode via an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset will generate a device initialisation, while a WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for the device reset can be determined. The PDF flag is cleared by a system power-up or by executing the CLR WDT instruction, and is set by fS A WDT time-out when the device is in the Power Down mode differs from other device reset conditions, as it will perform a warm reset that resets only the program counter and the SP but leaves the other circuits in their original state. Some registers remain unaffected during other reset conditions. Most registers are reset to their initial condition once the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between the different types of device resets. D iv id e r RT2 RT1 RT0 P r e s c a le r 8 to 1 M ux. 2 8/fS ~ 2 15/fS R T C In te rru p t Real Time Clock Rev. 1.00 15 December 19, 2006 HT46R652 TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up WDT time-out during normal operation WDT Wake-up 10kW 0 .1 m F * 100kW RES V DD 0 .0 1 m F * Note: u stands for unchanged To guarantee that the system oscillator is started and stabilised, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the Power Down mode or during a power up. When awakened from the Power Down mode or during a system power-up, the SST delay will be added. An extra SST delay is added during the power-up period, and any wake-up from the Power Down mode may enable only the SST delay. The following table shows how various components of the microcontroller are affected after a power-on reset occurs. Program Counter Interrupt Prescaler, Divider WDT, RTC, Time Base Timer/event Counter Input/output Ports Stack Pointer 000H Disabled Cleared Cleared. After master reset, WDT starts counting Off Input mode Points to the top of the stack OSC1 RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n HALT W DT W DT T im e - o u t R eset E x te rn a l C o ld R eset W a rm R eset Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. VDD RES S S T T im e - o u t C h ip R eset tS ST + tO PD Reset Timing Chart Reset Configuration Rev. 1.00 16 December 19, 2006 HT46R652 The register states are summarised in the following table: Register TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 BP ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA PAC PB PBC PC PCC PD PDC PWM0~ PWM15 ADRL ADRH ADCR ACSR Note: Reset (Power On) xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 RES Reset (HALT) xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 -000 -000 --00 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 ---- --00 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu u--0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu -uuu -uuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu ---- --uu Rev. 1.00 17 December 19, 2006 HT46R652 Timer/Event Counter Two timer/event counters, Timer/Event Counter 0 and Timer/Event Counter,1 are implemented within the microcontroller. Timer/Event Counter 0 is a 16-bit programmable count-up counter whose clock may come from an external or internal source. The internal clock source will come from fSYS. Timer/Event Counter 1 is also a 16-bit programmable count-up counter whose clock may come from an external source or an internal source. The internal clock source comes from fSYS/4 or a 32768Hz source, selected by a configuration option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are three registers associated with Timer/Event Counter 0; TMR0H, TMR0L and TMR0C, and another three for Timer/Event Counter 1; TMR1H, TMR1L and TMR1C. Writing to TMR0L and TMR1L will only put the written data into an internal lower-order byte buffer (8-bit) while writing to TMR0H and TMR1H will transfer the specified data and the contents of the lower-order byte buffer to the TMR0H/TMR1H and TMR0L/TMR1L registers. The Timer/Event Counter 0/1 preload register is changed with each TMR0H/TMR1H write operations. Reading TMR0H/TMR1H will latch the contents of TMR0H/TMR1H and TMR0L/TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading TMR0L/TMR1L will only read the contents of the lower-order byte buffer. The TMR0C and TMR1C registers are the Timer/Event Counter control registers, which control the operating mode, the timer enable or disable and the active edge type. The T0M0, T0M1 and T1M0, T1M1 bits define the timer operational mode. The event count mode is used to count external events, which requires that the clock source comes from an external TMR0 or TMR1 pin. The timer mode functions as a normal timer with the clock source coming from the internally selected clock source. The pulse width measurement mode can be used to count the high or low level duration of an external signal on pin TMR0 or TMR1, with the count value based on the internally selected clock source. In the event count or timer mode, the timer/event counter starts counting from the current contents in the D a ta B u s fS YS 8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l f IN T L o w B y te B u ffe r T0M 1 T0M 0 1 6 - B it P r e lo a d R e g is te r R e lo a d H ig h B y te L o w B y te PFD0 O v e r flo w to In te rru p t 1 6 - B it T im e r /E v e n t C o u n te r Timer/Event Counter 0 D a ta B u s fS /4 M U X TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l L o w B y te B u ffe r T YS f IN 32768H z T1S T1M 1 T1M 0 1 6 - B it P r e lo a d R e g is te r R e lo a d H ig h B y te L o w B y te PFD1 O v e r flo w to In te rru p t 1 6 - B it T im e r /E v e n t C o u n te r Timer/Event Counter 1 PFD0 M PFD1 U X 1 /2 PFD P A 3 D a ta C T R L PFD S o u r c e O p tio n PFD Source Option Rev. 1.00 18 December 19, 2006 HT46R652 timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag, T0F; bit 6 of INTC0 and T1F; bit 4 of INTC1. In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 or TMR1 pin has received a transient from low to high, or high to low if the T0E/T1E bit is 0, it will start counting until the TMR0 or TMR1 pin returns to its original level and resets the T0ON/T1ON bit. The measured Bit No. Label To define the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1: count on falling edge; 0: count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode T0M1, T0M0= 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR0C (0EH) Register Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1: count on falling edge; 0: count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0= disabled; 1= enabled) Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz) Defines the operating mode T1M1, T1M0= 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C (11H) Register Rev. 1.00 19 December 19, 2006 Function result remains in the timer/event counter even if the activated transient occurs again. In other words, only a single measurement can be made until the T0ON/T1ON is again set. In this operation mode, the timer/event counter begins counting, not according to the logic level on the pins, but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. Function 0 1 2 T0PSC0 T0PSC1 T0PSC2 3 T0E 4 5 T0ON 3/4 6 7 T0M0 T0M1 3 T1E 4 5 T1ON T1S 6 7 T1M0 T1M1 HT46R652 To enable a counting operation, the Timer ON bit, T0ON or T1ON should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be used to drive the PFD (Programmable Frequency Divider) output on pin PA3, a function which is selected by a configuration option. If PA3 is setup as a PFD output, there are two types of selections. One is to use PFD0 as the PFD output, the other is to use PFD1 as the PFD output. PFD0 and PFD1 are the timer overflow signals of the Timer/Event Counter 0 and Timer/Event Counter 1 respectively. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing a SET [PA].3 instruction will enable the PFD output and executing a CLR [PA].3 instruction will disable the PFD output. In cases where the timer/event counter is turned off, writing data to the timer/event counter preload register will also reload the new data into the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter will only be stored in the timer/event counter preload register. The timer/event counter will continue with its normal operation until an overflow occurs. When the timer/event counter is read, the clock is blocked to avoid errors, which may result in a counting error and should therefore be taken into account by the programmer. It is strongly recommended to load a desired value into the timer registers first before turning on the related timer/event counter, for proper operation since the initial value of the timer registers is unknown. Due to the timer/event counter scheme, the programmer should pay special attention with instructions to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable results. After this procedure, the timer/event function can be operated normally. Bits 0~2 of TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The overflow signal of the timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the the PWM counter. Input/Output Ports There are 32 bidirectional input/output lines in the microcontroller, divided among several ports labeled as PA, PB, PC and PD. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m]. For output operations, all the data is latched and reRev. 1.00 20 mains unchanged until the output latch is rewritten. Each port has has its own Port Control Register, known as PAC, PBC, PCC and PDC to control the input/output configuration. With this control register, a CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding bit of the control register must contain a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-mod ify-write instruction. After a device reset, as the Port Control Registers will be set high, the input/output lines will be setup as inputs, and will be at a high level or in a floating state, depending on the pull-high configuration options. Each bit of these input/output latches can be set or cleared by the SET [m].i and CLR [m].i instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has pull-high options. Once the pull-high option is selected, the I/O port has a pull-high resistor. It should be noted that a non-pull-high I/O port operating in an input mode will be in a floating condition. Pin PA3 is pin-shared with the PFD signal. If the PFD configuration option is selected, the output signal for PA3, if it setup as an output, will be the PFD signal generated by the timer/event counter overflow signal. If setup as an input the PA3 will always retain its input function. Once the PFD configuration option is selected, the PFD output signal can be controlled by the PA3 data register. Writing a 1 to the PA3 data register will enable the PFD output function while writing a 0 will force the PA3 pin to remain in a low condition. The I/O functions of the PA3 pin are shown in the table. I/O I/P Mode (Normal) PA3 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) The PFD frequency is the timer/event counter overflow frequency divided by 2. Pins PA0, PA1, PA3, PA5, PA6, PA4 and PA7 are pin-shared with the BZ, BZ, PFD, INT0, INT1, TMR0 and TMR1 pins respectively. The PA0 and PA1 pins are pin-shared with the BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in the output mode of PA0/PA1 will be the buzzer signal, which is generated by the multi-funcDecember 19, 2006 HT46R652 V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK Q S Q PU PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PC0 PD0 M U X PFDEN (P A 3 ) U X O P0~O P7 /B Z /B Z /P /T /IN /IN /T /A /P /P FD MR0 T0 T1 MR1 N 0 ~ P B 7 /A N 7 W M 0 ~ P C 7 /P W M 7 W M 8 ~ P D 7 /P W M 1 5 DD D a ta B it Q D CK S Q W r ite D a ta R e g is te r P A 0 /P A 1 /P A 3 /P C 0 ~ P C 7 /P D 0 ~ P D 7 B Z /B Z /P F D /P W M 0 ~ P W M 7 /P W M 8 ~ P W M 1 5 M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) TM IN IN TM R0 T0 T1 R1 fo fo fo fo rP rP rP rP A4 A5 A6 A7 on on on on ly ly ly ly Input/Output Ports tion timer. If the pins are setup as inputs then they will always retain their input function. Once the BZ/BZ configuration option is selected, the buzzer output signal is controlled by the PA0/PA1 data register. The PA0/PA1 pins I/O functions are shown in the table. PA0 I/O PA1 I/O PA0 Mode PA1 Mode PA0 Data PA1 Data PA0 Pad Status PA1 Pad Status Note: I I I O OOOOOOOO I I I OOOOO I/O Mode PC0~PC7, PD0~PD7 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0~ PWM15 XXCBBCBBBB XCXXXCCCBB XXD0 1 D0 0 1 0 1 Any unused pins must be carefully managed to ensure that there are no floating input lines which will result in increased power consumption. It is therefore recommended that any unused pins are setup as outputs or connected to a pull-high resistor if setup as inputs. The definitions of the PFD control signals and the PFD output frequencies are listed in the following table. PA3 Timer Data Timer Preload Value Register OFF OFF ON ON Note: X X N N 0 1 0 1 PA3 Pad State 0 U 0 PFD PFD Frequency X X X fTMR/[2(M-N)] X D X X X D1 D D X X I I I D D0 I I B D0 0 B 0 B B I D1 D D 0 I input; O output; D, D0, D1 Data B buzzer option, BZ or BZ X dont care; C CMOS output The PB port is also used for the A/D converter inputs. The PWM outputs are shared with pins PC0~PC7 and PD0~PD7. If the PWM function is enabled, the PWM0~PWM15 outputs will appear on pins PC0~PC7 and PD0~PD7, if PC0~PC7 and PD0~PD7 are setup as outputs. Writing a 1 to the PC0~PC7 and PD0~PD7 data registers will enable the PWM output function while writing a 0 will force PC0~PC7 and PD0~PD7 to remain at a 0level. The I/O functions of PC0~PC7 and PD0~PD7 are shown in the table. X stands for unused U stands for unknown M is 65536 for PFD0 or PFD1 N is the timer/event counter preload value fTMR is the input clock frequency for the timer/event counter Rev. 1.00 21 December 19, 2006 HT46R652 PWM The microcontroller provides a 16-channel PWM output shared with pins PC0~PC7 and PD0~PD7. Its output signals can be configured as (6+2) or (7+1) type dependent upon configuration options. Each PWM channel has its own 8-bit data register, denoted as PWM0~PWM15. The PWM frequency source comes from fSYS. Once the PC0~PC7 and PD0~PD7 pins are selected as PWM outputs, if the pins are setup as outputs, writing a 1 to the PC0~PC7 and PD0~PD7 data registers will enable the corresponding PWM output function, while writing a 0 will force the PC0~PC7 and PD0~PD7 pins to remain at 0. In the (6+2) mode, the PWM cycle is divided into four modulation cycles, modulation cycle 0~modulation cycle 3. Each modulation cycle has 64 PWM input clock periods. In the (6+2) mode, the contents of each PWM register is divided into two groups. Group 1 of the PWM register is denoted by a DC which is the value of PWM.7~PWM.2. Group 2 is denoted by AC which is the fS YS value of PWM.1~PWM.0. In the (6+2) mode, the duty cycle of each modulation cycle is shown in the table. Parameter Modulation cycle i (i=0~3) AC (0~3) i /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 YS 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 M o d u la tio n c y c le 1 PW M 2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS YS 2 5 /6 4 M o d u la tio n c y c le 3 2 6 /6 4 M o d u la tio n c y c le 0 (6+2) PWM Mode fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS YS YS 5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 2 /1 2 8 M o d u la tio n c y c le 1 M o d u la tio n c y c le 0 (7+1) PWM Mode Rev. 1.00 22 December 19, 2006 HT46R652 Parameter Modulation cycle i (i=0~1) AC (0~1) i Bit No. Label Function Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined Unused bit, read as 0 ACSR (27H) Register 0 1 ADCS0 ADCS1 3/4 2~7 Rev. 1.00 23 December 19, 2006 HT46R652 Bit No. 0 1 2 3 4 5 6 Label ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 EOCB Defines the analog channel select. Function Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation. Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Resets the A/D converter and sets EOCB to 1) ADCR (26H) Register 7 START PCR2 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 1 7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7 6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6 5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5 4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4 3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3 2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2 1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1 0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 Port B Configuration ACS2 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 Analog Input Channel Selection Register ADRL ADRH Bit7 D3 D11 Bit6 D2 D10 Bit5 D1 D9 Bit4 D0 D8 Bit3 3/4 D7 Bit2 3/4 D6 Bit1 3/4 D5 Bit0 3/4 D4 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Note: D0~D11 is the A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register Rev. 1.00 24 December 19, 2006 HT46R652 The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion clr mov mov mov mov EADI a,00000001B ACSR,a a,00100000B ADCR,a : : ; disable ADC interrupt ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp start_conversion ; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect an end of A/D conversion ; continue polling ; read the conversion result high byte value from the ADRH register ; save result to the user defined memory ; read the conversion result low byte value from the ADRL register ; save the result to the user defined memory ; start the next A/D conversion M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D s a m p lin g tim e tA D C S 000B 100B A /D tA DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 101B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D tA D tA CS 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C c o n v e r s io n tim e YS A /D tA D C c o n v e r s io n tim e A /D DC c lo c k m u s t b e fS = 3 2 tA D = 8 0 tA D YS /2 , fS /8 o r fS YS /3 2 A/D Conversion Timing Rev. 1.00 25 December 19, 2006 HT46R652 LCD Display Memory The device provides an area of embedded data memory for the LCD display. This area is located from 40H to 68H of the Data Memory inside Bank 1. The Bank Pointer, known as BP, is used to select the LCD display memory. When the BP is set to 1, any data written into locations 40H~68H will affect only the LCD display. When the BP is cleared to 0 or set to 2, any data written into locations 40H~68H will access the general purpose data memory. The LCD display memory can be read and written to only by an indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. LCD Driver Output The output number of the device LCD driver can be 412 or 413 or 404 by option, i.e., 1/2 duty, 1/3 duty or COM 0 1 2 3 3 2 40H 41H 42H 43H 66H 67H 68H B it 0 1 SEGMENT 0 1 2 3 38 39 40 Display Memory 1/4 duty. The LCD driver can either have an R type or C bias type. If the R bias type is selected, no external capacitors are required. If the C bias type is selected, a capacitor is required to be connected between the C1 and C2 pins. The LCD driver bias voltage can be 1/2 bias or 1/3 bias, selected via a configuration option. If the 1/2 bias is selected, a capacitor must be connected between the V2 pin and ground. If the 1/3 bias is selected, two capacitors are needed for the V1 and V2 pins. VA VB VC VSS VA VB VC COM1 VSS VA VB VC COM2 VSS VA VB COM3 VC VSS VA VB L C D s e g m e n ts O N C O M 2 s id e lig h te d N o te : 1 /4 d u ty , 1 /3 b ia s , C 1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D VC VSS COM0 LCD Driver Output Rev. 1.00 26 December 19, 2006 HT46R652 D u r in g a R e s e t P u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts * * * VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS VL 1 /2 VS CD S CD S VLC D VLC D N o r m a l O p e r a tio n M o d e COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 , 2 s id e s a r e lig h te d HALT M ode CO M 0,CO M 1,CO M 2 A ll lc d d r iv e r o u tp u ts CD CD S S VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D VLC D CD CD S S CD CD S CD S S CD S CD CD S VLC D S CD VLC D S CD CD S S VLC D VLC D N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . LCD Driver Output - 1/3 Duty, 1/2 Bias, R/C Type LCD Segments as Logic Outputs The SEG0~SEG23 pins can also can be setup as logic outputs via a configuration options. Once an LCD segment is configured as a logic output, the content of bit0 of the related segment address in the LCD RAM will appear on the segment. Pins SEG0~SEG7 and SEG8~SEG15 are together byte optioned as logic outputs, SEG16~SEG23 are individually bit optioned as logic outputs. LCD Type LCD Bias Type VMAX R Type 1/2 bias 1/3 bias 1/2 bias C Type 1/3 bias 3 If VDD> VLCD, then VMAX connect to VDD, 2 else VMAX connect to V1 If VDD>VLCD, then VMAX connect to VDD, else VMAX connect to VLCD Rev. 1.00 27 December 19, 2006 HT46R652 Low Voltage Reset/Detector Functions A low voltage detector, LVD, and low voltage reset, LVR, functions are implemented within the microcontroller. These two functions can be enabled/disabled by options. Once the LVD option is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. The RTCC register definitions are listed below. Bit No. 0~2 3 4 5 6, 7 Label RT0~RT2 LVDC QOSC LVDO 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillator 0/1: quickly/slowly start LVD detection output (1/0) 1: low voltage detected, read only Unused bit, read as 0 RTCC (09H) Register The LVR has the same effect or function as the external RES signal which performs a chip reset. During the HALT state, both LVR and LVD are disabled. The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in its origi- The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V V 3 .0 V 2 .2 V LVR nal state for longer than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function. * The LVR uses an OR function with the external RES 0 .9 V Note: VOPR is the voltage range for proper chip operation with a 4MHz system clock. signal to perform a chip reset. V 5 .5 V DD V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting normal operation. *2: Since a low voltage state has to be maintained its original state for over tLVR, therefore after tLVR delay, the device enters the reset mode. Rev. 1.00 28 December 19, 2006 HT46R652 Configuration Options The following shows the configuration options in the device. All these options must be defined in order to ensure proper functioning of the microcontroller. Options OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as the system clock. WDT, RTC and time base clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or 215/fS~216/fS. CLR WDT times selection. This option defines the method to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, the WDT can be cleared. Time Base time-out period selection. The Time Base time-out period ranges from 212/fS to 215/fS. fS means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/22~fS/29. fS means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge (bit option). Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. PA, PB, PC and PD can be independently selected (bit option). I/O pins shared with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or as buzzer outputs. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin SEG40 will be setup as a common output. LCD bias power supply selection. There are two types of selections: 1/2 bias or 1/3 bias LCD bias type selection. This option is to determine what kind of bias is selected, R type or C type. LCD driver clock frequency selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS stands for the clock source selection by options. LCD ON/OFF at HALT selection. LCD Segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option) [SEG0~SEG7], [SEG8~SEG15], SEG16, SEG17, SEG18, SEG19, SEG20, SEG21, SEG22, or SEG23 LVR selection. LVR enable\disable option LVD selection. LVD enable\disable option PFD selection. If PA3 is setup as a PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0 and Timer/Event Counter 1, respectively. PWM selection: (7+1) or (6+2) mode PC0~PC7: General Purpose I/Os or PWM outputs (port option - no individual pin selection) PD0~PD7: General Purpose I/O or PWM output (bit option - individual pin selection) INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low. LCD bias current selection: low/high driving current (for R type only). Rev. 1.00 29 December 19, 2006 HT46R652 Application Circuits V DD 0 .0 1 m F * 100kW 0 .1 m F 10kW VDD RES CO M 0~CO M 2 C O M 3 /S E G 4 0 SEG 0~SEG 39 VLC D VMAX LCD PANEL LCD P o w e r S u p p ly 0 .1 m F * VSS C1 0 .1 m F C2 V DD OSC C ir c u it S e e r ig h t s id e 32768H z 10pF OSC1 OSC2 V1 0 .1 m F R V2 0 .1 m F 470pF OSC OSC1 fS YS R C S y s te m O s c illa to r 24kW OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r C1 OSC3 OSC4 P PA P P PA P C 0 /P W M 0 P C 7 /P W M 7 P D 0 /P W M 8 P D 7 /P W M 1 5 ~ ~ P A 0 /B P A 1 /B PA A 3 /P F 4 /T M R A 5 /IN T A 6 /IN T 7 /T M R D ~ Z Z 2 0 0 1 1 C2 R1 OSC2 OSC1 P B 0 /A N 0 P B 7 /A N 7 OSC2 OSC 32 Os OS un 7 6 8 H z C ry s ta l S y s te m c illa to r C 1 a n d O S C 2 le ft c o n n e c te d H T46R 652 C ir c u it The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 400kHz Resonator C1, C2 25pF 10pF 25pF 10pF 25pF 68pF 100pF 200pF 200pF 300pF R1 12kW 18kW 12kW 15kW 12kW 24kW 12kW 12kW 12kW 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. VMAX connect to VDD or VLCD or V1 refer to the table. LCD Type LCD bias type VMAX R Type 1/2 bias 1/3 bias 1/2 bias If VDD>VLCD, then VMAX connect to VDD, else VMAX connect to VLCD C Type 1/3 bias If VDD > 3/2VLCD, then VMAX connect to VDD, else VMAX connect to V1 Rev. 1.00 30 December 19, 2006 HT46R652 Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.00 31 December 19, 2006 HT46R652 Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.00 32 December 19, 2006 HT46R652 Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.00 33 December 19, 2006 HT46R652 AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 34 December 19, 2006 HT46R652 CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) CLR WDT1 Description Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR WDT2 Description Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 35 December 19, 2006 HT46R652 CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Operation Affected flag(s) Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 DECA [m] Description Operation Affected flag(s) Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 36 December 19, 2006 HT46R652 HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.00 37 December 19, 2006 HT46R652 MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.00 38 December 19, 2006 HT46R652 RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RETI Description Operation Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RL [m] Description Operation Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RLA [m] Description Operation Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 39 December 19, 2006 HT46R652 RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) RR [m] Description Operation Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRA [m] Description Operation Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRC [m] Description Operation Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rev. 1.00 40 December 19, 2006 HT46R652 RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Rev. 1.00 41 December 19, 2006 HT46R652 SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SNZ [m].i Description Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 42 December 19, 2006 HT46R652 SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 43 December 19, 2006 HT46R652 SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) TABRDL [m] Description Operation Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.00 44 December 19, 2006 HT46R652 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.00 45 December 19, 2006 HT46R652 Package Information 100-pin QFP (1420) Outline Dimensions C D 80 51 G H I 81 50 F A B E 100 31 K 1 30 a J Symbol A B C D E F G H I J K a Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7 Rev. 1.00 46 December 19, 2006 HT46R652 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 47 December 19, 2006 |
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